Field of Invention
This invention relates to a device in an integrate circuit and fabrication thereof, and particularly relates to a capacitor structure, especially a storage capacitor structure of DRAM, and to a process for fabricating the capacitor structure.
Description of Related Art
A conventional DRAM cell includes a transistor and a capacitor coupled thereto. In certain types of capacitor processes of DRAM, the lower electrodes of the capacitors of the memory cells are formed in straight-sidewall openings in a template layer, and then the template layer is entirely removed to maximize the exposed surface area of each lower electrode, thereby maximizing the capacitance of the capacitor formed later.
Because the integration degree of DRAM is raised gradually, the lateral area of each memory cell or each lower electrode is decreased gradually, and the height of each lower electrode has to be increased to maintain the capacitance of the capacitor beyond a certain level. Due to the increase in the aspect ratio, the straight-sidewall lower electrodes formed in the straight-sidewall openings in the template layer have lower mechanical strength, and are more easily damaged in the steps performed after the template layer is removed.